The present embodiments relate to radio frequency identification (RFID) circuitry and, more particularly, to an ultra-low power, high dynamic range data detector for a UHF RFID circuit.
Radio frequency identification (RFID) circuits or transponders are prevalent in business, personal, and other applications, and as a result the technology for such devices continues to advance in various areas. Numerous applications for RFID circuits include automatic vehicle identification (AVI) for toll booth systems, smart card systems, book identification for libraries, pet identification systems, and inventory control. All of these systems include an interrogator and an RFID transponder. The interrogator must activate the transponder within a certain range, interrogate the transponder for specific information, and acknowledge receipt of the information. There are several advantages of the RFID circuit. First, it does not require an optical link. Thus, it can be implanted for pet identification or in a person to provide medical information. Second, it is typically powered by a received continuous wave (CW) signal from the interrogator and is, therefore, virtually maintenance free. Finally, the RFID transponder preferably communicates with the interrogator by backscattering. The transponder operates in resonance with the interrogator, modulates the original CW transmission, and sends it back to the interrogator. Thus, the RFID transponder emits no radio frequency signals until it is within range of a corresponding interrogator. A detailed specification of such an RFID system is described at “EPC™ Radio-Frequency Identity Protocols, Class-1 Generation-2 UHF RFID,” Version 1.0.9, January 2005, and incorporated herein by reference in its entirety.
There are three major problems associated with existing data detector schemes. The first and most common problem is poor large RF signal handling capability. Referring to FIG. 9, there is an exemplary Schottkey full wave rectifier circuit of the prior art. The full wave rectifier circuit rectifies an RF input signal having −Vp to +Vp voltage excursion. The rectified voltage is then converted to a digital signal by a data slicer. The data slicer is typically a latched comparator that derives its power from the rectified supply voltage Vdd. Hence, it can only handle RF signals within a certain range. To give representative numbers, if the Vdd is 1.35V, then a large RF signal of value 1.8V peak at the RFID transponder input can result in a voltage as high as 3V at the input of the data slicer. This is more than twice the supply voltage and is too much for it to handle. The reason for a value as high as 3V is that the rectifier stage behaves like a voltage doubler. For example, at −Vp, diode 902 charges capacitor 900 to Vp-Vd as shown. Then at +Vp, diode 906 charges capacitor 908 to Vp-Vd. At −Vp of the next cycle, diode 902 again charges capacitor 900 to Vp-Vd. But on the following Vp, diode 906 charges capacitor 908 to 2(Vp-Vd) as shown.
A second problem with data detectors of the prior art is a difficulty interpreting small RF signals. Referring to FIG. 10, there is a simplified schematic diagram of a data slicer circuit of the prior art. Antenna 1000 receives a modulated RF input signal. RF clamp 1006 limits the peak-to-peak voltage excursion of the RF input signal to avoid damage to internal circuits. Multi-stage rectifier 1002 rectifies the RF signal. The rectified RF signal is regulated by voltage regulator 1004 to produce a nominal supply voltage Vdd of 1.35V. The RF input signal is also applied to single stage rectifier 1008 in the data path. The rectifier output produces an envelope difference voltage 1016 across resistor 1012 at the inputs of comparator 1014. The problem here is in the way the data slicing is traditionally done. Since the data information is contained in the signal envelope 1016, the signal envelope is compared with the average 1018 over several cycles to determine whether the data is a data-1 or a data-0. Ideally, the desired average would be half way between the maximum and minimum values of the signal envelope. Then the differential voltage across the inputs of comparator 1014 is symmetric. For example, the differential input might be +0.1V for a data-1 and −0.1V for a data-0. However, this is not usually the case as illustrated at FIG. 11. A maximum value of the signal envelope has the lowest value when the RF signal is minimum (Vp is minimum) and the diode drop is maximum (−40 deg C. and worst corner for diode). Under these circumstances the signal envelope peak can have a value as low as 40 mV. Further, depending on the encoding scheme, the data-1 and the data-0 can look as shown in FIG. 11, with very little time when RF is absent. This encoding scheme is particularly suitable for low RF conditions, when the RF power transmitted is small and it is desirable to have RF energy available to the RFID transponder for a greater fraction of the time. Under such a situation, when the data consists of a large number of data-1s, the average gravitates close to the maximum value of the signal envelope and can have a value as high as 35 mV. The difference between the envelope and the average is what the data slicer resolves to determine if it is a data-1 or data-0. This value can then be 5 mV and it can often be smaller than the comparator offset. Of course, this produces a wrong detection for a data-1.
Finally, the third major problem with data detectors of the prior art is large power consumption. Data detectors of the prior art typically use a comparator with buffered output 1216 as shown at FIG. 12. The output 1216 is typically latched by a D-flip flop (not shown). The comparator includes N-channel input transistors 1200 and 1202 and P-Channel current mirror transistors 1204 and 1206. The comparator further includes start up circuit 1208 and output transistors 1212 and 1214. Tail current through the comparator is determined by N-channel transistor 1210. In operation, a difference voltage at N-channel input transistors 1200 and 1202 produces a comparator output voltage at node A. The slew rate at node A must be sufficient to present a correct digital signal at the D-flip flop input prior to latch activation. Frequently, the desired slew rate at node A, therefore, requires relatively high comparator tail current and large power consumption.
In view of the preceding problems, the present inventors recognize that further improvements may be made by addressing some of the drawbacks of the prior art. In particular, there is a need to improve data detection over all operating conditions without excessive power consumption of the RFID transponder. Accordingly, the preferred embodiments described below are directed toward these benefits as well as improving upon the prior art.